1. Field of the Invention
This invention relates to an operational amplifier including a differential amplification circuit of a cascode connection type.
2. Description of the Related Art
Japanese patent application publication number 58-218225 discloses a MOS transistor amplifier designed to operate at an increased speed. The amplifier in Japanese application 58-218225 includes a differential amplification circuit, a first MOS transistor, a capacitor, a second MOS transistor, and a switch. The gate of the first MOS transistor is connected with the output terminal of the differential amplification circuit. One end of the capacitor is connected with the output terminal of the differential amplification circuit, and with the gate of the first MOS transistor. The other end of the capacitor is connected with the gate of the second MOS transistor. The switch is used in controlling the application of a bias voltage to the gate of the second MOS transistor. When the switch is in its on state, the voltage at the gate of the second MOS transistor is fixed to a level provided by a bias circuit. When the switch is in its off state, a variation in the voltage at the output terminal of the differential amplification circuit is transmitted to the gates of the first and second MOS transistors. During a time interval immediately before a pulse voltage inputted to the differential amplification circuit rises, the switch is held in its on state to charge the capacitor. Also, during a time interval immediately before the pulse voltage drops, the switch is held in its on state to charge the capacitor. During other time intervals, the switch is held in its off state.
Japanese patent application publication number 6-152274 discloses an amplifier including a first differential amplification circuit, a first emitter follower circuit, a second differential amplification circuit, a second emitter follower circuit, and a bias circuit. The first differential amplification circuit, the first emitter follower circuit, the second differential amplification circuit, and the second emitter follower circuit are sequentially connected in that order. The bias circuit applies a bias voltage to the base of a transistor within the second differential amplification circuit. The bias circuit includes a capacitor connected between a power feed line and the base of the transistor.
U.S. Pat. No. 4,538,114 corresponding to Japanese patent application publication number 59-43614 discloses a differential amplifier formed of MISFETs. The differential amplifier in U.S. Pat. No. 4,538,114 includes a differential amplification stage and a pair of cascode amplification stages which receive outputs from the differential amplification stage. In each of the cascode amplification stages, an amplifying MISFET which receives an input signal at its source has a channel conductivity of a type opposite to that of the differential input MISFETs of the differential amplification stage. The differential amplifier has good frequency characteristics. Since the pair of cascode amplification stages make the currents taken from a pair of outputs from the differential amplification stage equal to each other, the operating balance of the differential amplification stage is not affected. The differential amplifier further includes a feedback circuit which detects the operating points of the cascode amplification stages by referring to the outputs of the cascode amplification stages, and generates a control voltage by comparing the detected operating points with a reference potential. The control voltage is fed back to the gates of the amplifying MISFETs in each cascode amplification stage. As a result, the operating point of each cascode amplification stage can be stabilized irrespective of variations in the characteristics of the MISFETs.
The differential amplifier in U.S. Pat. No. 4,538,114 further includes a bias circuit for applying a constant voltage to a MISFET in the differential input stage to make the MISFET operate as a constant-current source. The bias circuit also applies the constant voltage to MISFETs in the cascode stage to make them operate as constant-current sources. Thereby, the cascode stage is biased.
European patent application publication number 0446652 A1 corresponding to Japanese patent application publication number 4-220806 discloses a CMOS transconductance operational amplifier. The operational amplifier in European application 0446652 A1 includes a first differential stage, and a second single-ended stage driven by the first differential stage. The first differential stage is formed by two transistors which are biased by a current source and which have a load constituted by a current mirror. The current mirror is formed by two transistors with an MCAS cascode. The second single-ended stage is formed by a transistor which is biased by a current source. For frequency compensation, a first capacitor is connected between the source of the MCAS cascode of the first differential stage and the output node of the second single-ended stage, and a second capacitor is connected between the output node of the second single-ended stage and the input node of the second single-ended stage.
It is an object of this invention to provide an improved operational amplifier including a differential amplification circuit of a cascode connection type.
A first aspect of this invention provides an operational amplifier comprising a differential amplification circuit including load transistors arranged in a cascode connection; a voltage amplification circuit forming a stage following the differential amplification circuit; a capacitor coupling the differential amplification circuit and the voltage amplification circuit with each other; and a bias setting circuit for charging the capacitor to a prescribed bias voltage before amplification is started.
A second aspect of this invention is based on the first aspect thereof, and provides an operational amplifier wherein the charged capacitor sets the differential amplification circuit in a prescribed biased state.
A third aspect of this invention is based on the first aspect thereof, and provides an operational amplifier wherein the capacitor is interposed in a connection path between an output terminal of the differential amplification circuit and an input terminal of the voltage amplification circuit.
A fourth aspect of this invention is based on the third aspect thereof, and provides an operational amplifier wherein the capacitor includes first and second terminals connected to the output terminal of the differential amplification circuit and the input terminal of the voltage amplification circuit respectively.
A fifth aspect of this invention is based on the fourth aspect thereof, and provides an operational amplifier wherein the voltage amplification circuit includes a transistor having a gate connected with the input terminal of the voltage amplification circuit, and the bias setting circuit comprises a first switch circuit for applying a first bias setting voltage to the first terminal of the capacitor, and a second switch circuit for applying a second bias setting voltage to the second terminal of the capacitor.
A sixth aspect of this invention is based on the fifth aspect thereof, and provides an operational amplifier wherein the second switch circuit is connected between the second terminal of the capacitor and a drain of the transistor.
A seventh aspect of this invention is based on the fifth aspect thereof, and provides an operational amplifier wherein the bias setting circuit further comprises a third switch circuit connected between the output terminal of the differential amplification circuit and the first terminal of the capacitor.
An eighth aspect of this invention is based on the fourth aspect thereof, and provides an operational amplifier wherein the voltage amplification circuit includes a first transistor having a gate connected with the input terminal of the voltage amplification circuit, and a second transistor connected in series with the first transistor, and further comprising a second capacitor connected between a gate of the second transistor and one of the first and second terminals of the capacitor coupling the differential amplification circuit and the voltage amplification circuit with each other, and a second bias setting circuit for charging the second capacitor to a prescribed bias voltage before amplification is started.
A ninth aspect of this invention is based on the first aspect thereof, and provides an operational amplifier wherein the voltage amplification circuit has a plurality of input terminals and the differential amplification circuit has an output terminal, and the output terminal of the differential amplification circuit is connected with the input terminals of the voltage amplification circuit via a plurality of capacitors including the capacitor coupling the differential amplification circuit and the voltage amplification circuit with each other.
A tenth aspect of this invention provides an operational amplifier comprising a differential amplification circuit including load transistors arranged in a cascode connection; a voltage amplification circuit forming a stage following the differential amplification circuit; a capacitor coupling the differential amplification circuit and the voltage amplification circuit with each other; first means for charging the capacitor into a charged state during a first term; and second means for holding the capacitor in the charged state during a second term after the first term.
An eleventh aspect of this invention provides an operational amplifier comprising a differential amplification circuit including load transistors arranged in a cascode connection; a voltage amplification circuit forming a stage following the differential amplification circuit; first and second transistors included in the voltage amplification circuit and connected in series, the first transistor being of a first conductivity type, the second transistor being of a second conductivity type opposite to the first conductivity type; a first capacitor coupling the differential amplification circuit and the first transistor with each other; first means for charging the first capacitor into a charged state during a first term; second means for holding the first capacitor in the charged state during a second term after the first term; a second capacitor coupling the differential amplification circuit and the second transistor with each other; third means for charging the second capacitor into a charged state during the first term; and fourth means for holding the second capacitor in the charged state during the second term.